(a) Field of the Invention
The present invention relates to a plasma display panel (PDP) and a driving method thereof.
(b) Description of the Related Art
Recently, liquid crystal displays (LCDs), field emission displays (FEDs), and PDPs have been actively developed. The PDPs from among the flat panel devices have better luminance and light emission efficiency compared to the other types of flat panel devices, and also have wider view angles. Therefore, the PDPs have come into the spotlight as substitutes for the conventional cathode ray tubes (CRTs) in large displays of greater than 40 inches.
A PDP is a flat display for showing characters or images using plasma generated by gas discharge, and pixels numbering to more than several million are provided thereon in a matrix format, according to its size. Referring to FIGS. 1 and 2, a PDP structure will now be described.
FIG. 1 shows a partial perspective view of the PDP. FIG. 2 shows an electrode arrangement of the PDP.
As shown in FIG. 1, the PDP includes glass substrates 1 and 6 facing each other with a predetermined gap therebetween. Scan electrodes 4 and sustain electrodes 5 in pairs are formed in parallel on glass substrate 1. Scan electrodes 4 and sustain electrodes 5 are covered with dielectric layer 2 and protection film 3. A plurality of address electrodes 8 is formed on glass substrate 6. Address electrodes 8 are covered with an insulator layer 7. Barrier ribs 9 are formed on insulator layer 7 between address electrodes 8. Phosphors 10 are formed on the surface of insulator layer 7 and between barrier ribs 9. Glass substrates 1 and 6 are provided facing each other with discharge spaces therebetween so that scan electrodes 4 and sustain electrodes 5 may respectively cross address electrodes 8. Discharge space 11 between address electrodes 8 and a crossing part of the paired scan electrode 4 and sustain electrode 5 forms discharge cell 12.
As shown in FIG. 2, the electrodes of the PDP have an (n×m) matrix format. Address electrodes Al through Am are arranged in the column direction, and n scan electrodes Y1 through Yn and n sustain electrodes X1 through Xn are arranged in pairs in the row direction.
Referring to FIGS. 3 and 4A through 4D, a conventional PDP driving method will be described.
FIG. 3 shows a driving waveform diagram of the conventional PDP, and FIGS. 4A through 4D show distributions of wall charges in respective intervals when using the conventional driving method. That is, FIGS. 4A through 4D show charge distributions corresponding to the driving waveform shown in FIG. 3.
In general, a single frame is divided into a plurality of subfields in the PDP, and the gray is represented by combination of the subfields. As shown in FIG. 3, each subfield has a reset period, an address period, and a sustain period. In the reset period, wall charges formed by previous sustaining are erased, and the wall charges are set up so as to stably perform the next addressing. In the address period, cells that are turned on and those that are turned off are selected, and the wall charges are accumulated to the cells that are turned on (i.e., addressed cells). In the sustain period, sustaining is executed so as to display the actual image to the addressed cells.
When a sustain occurs in the sustain period, wall charges are formed and accumulated at the sustain and scan electrodes, and a discharge cell is sustained by a wall voltage formed by the wall charges and a sustain pulse alternately applied in the sustain period. Through the repetition of the above-noted process, a predetermined number of sustains occur in the sustain period. As described, the conventional method uses a memory function of the wall charges generated and stored at the scan and sustain electrodes to generate a sustain.
Referring to FIG. 3, the conventional reset period includes an erase period, a ramp rising period, and a ramp falling period.
(1) Erase Period
When the final sustain is finished, positive charges are accumulated to the sustain X electrode, and negative charges to the scan Y electrode, as shown in FIG. 4A. Since the address voltage is maintained at 0V (volts) during the sustain period, but it tries to maintain a middle voltage of the sustain all the time, a large amount of the positive charges are accumulated to the address A electrodes.
When the sustain is finished, an erase ramp voltage that gradually increases from 0(V) to+Ve(V) is applied to the sustain X electrode, and the wall charges formed on the sustain X and scan Y electrodes are gradually erased, as shown in FIG. 4B.
(2) Y Ramp Rising Period
During this period, the address A electrode and the sustain X electrode are maintained at 0V, and a ramp voltage is applied to the Y electrode, the ramp voltage gradually rising from voltage Vs that is below the discharge firing voltage with respect to the sustain X electrode to voltage Vset that is over the discharge firing voltage. While the ramp voltage rises, first weak resetting is generated to all the discharge cells from the scan Y electrode to the address A electrode and the sustain X electrode. As a result, the negative wall charges are accumulated to the scan Y electrode, and concurrently, the positive wall charges are accumulated to the address electrode and the sustain X electrode, as shown in FIG. 4C.
(3) Y Ramp Falling Period
In the latter part of the reset period, a ramp voltage that gradually falls from voltage Vs below the discharge firing voltage to 0(V) over the discharge firing voltage with respect to the sustain X electrode is applied to the scan Y electrode under the state that the sustain X electrode maintains a constant voltage Ve. While the ramp voltage falls, second weak resetting is generated from all the discharge cells. As a result, the negative wall charges of the scan Y electrode are reduced, and the polarity of the sustain X electrode is inverted to accumulate weak negative charges thereto, as shown in FIG. 4D. Also, the positive wall charges of the address A electrode are adjusted to an appropriate value for the address operation.
As described, the states of the sustain X electrode, the scan Y electrode, and the address A electrode are processed through the reset period so that they may be suitable for addressing in the address period. However, the address period is reduced because each subfield requires a reset period in the conventional driving method. A long address period is needed for scanning of a high-resolution screen, but it is not easy to display the high-resolution screen through the prior art. Also, discharges occur twice in the reset period, and hence, a constant discharge always exists in the discharge cells that are not turned on, and the total contrast of the screen is lowered.